You should use thermal paste to improve the heat dissipation. After the assembly , case construction is left to the builder. 100K potentiometers are used for adjusting the input volume. The potentiometers are absent in the layout. The 100K resistors need only be installed if the 100 K potentiometers are not used as shown in the layout. You should use a well designed quality transformer to get less noise. It will be another good way to use a sufficient battery to power the circuit. Keep the supply wires as short as possible. Input source should be isolated from the external noises too. It is recommended to use coaxial cable to connect the input audio.
Technical data:
As electrolytic capacitors age, their internal resistance, also known as "equivalent series resistance" (ESR), gradually increases. This can eventually lead to equipment failure. Using this design, you can measure the ESR of suspect capacitors as well as other small resistances. Basically, the schema generates a low-voltage 100kHz test signal, which is applied to the capacitor via a pair of probes. An op amp then amplifies the voltage dropped across the capacitor’s series resistance and this can be displayed on a standard multimeter. In more detail, inverter IC1d is configured as a 200kHz oscillator.
Its output drives a 4027 J-K flipflop, which divides the oscillator signal in half to ensure an equal mark/space ratio. Two elements of a 4066 quad bilateral switch (IC3c & IC3d) are alternately switched on by the complementary outputs of the J-K flipflop. One switch input (pin 11) is connected to +5V, whereas the other (pin 8) is connected to -5V. The outputs (pins 9 & 10) of these two switches are connected together, with the result being a ±5V 100kHz square wave. Series resistance is included to current-limit the signal before it is applied to the capacitor under test via a pair of test probes. Diodes D1 and D2 limit the signal swing and protect the 4066 outputs in case the capacitor is charged.
Circuit diagram:
ESR & Low Resistance Test Meter Circuit DiagramA second pair of leads sense the signal developed across the probe tips. Once again, the signal is limited by diodes (D3 & D4) before begin applied to the remaining two inputs of the 4066 switch (pins 2 & 3 of IC3a & IC3b). These switches direct alternate half cycles to two 1μF capacitors, removing most of the AC component of the signal and providing a simple "sample and hold" mechanism. The 1μF capacitors charge to a DC level that is proportional to the test capacitor’s ESR. This is differentially amplified by op amp IC4 so that it can be displayed on a digital multimeter – 10Ω will be represented by 100mV, 1Ω by 10mV, etc. To calibrate the schema, first adjust VR1 to obtain 100kHz at TP3.
Next, momentarily short the test probes together and adjust VR4 for 0mV at pin 6 of IC4. That done, set your meter to read milliamps and connect it between TP4 and the negative (-) DMM output. Apply -5V to TP2 and note the current flow, which should be around 2.1mA. Transfer the -5V from TP2 to TP1 and adjust VR2 until the same current (ignore sign) is obtained. Remove the -5V from TP1. Again, set to your meter to read volts and connect it to the DMM outputs. Apply the probes to a 10W resistor and adjust VR3 for a reading of 100mV. Finally, ensure that all capacitors to be tested are always fully discharged before connecting the probes.
Author: Len Cox - Copyright: Silicon Chip Electronics
